It is known to provide an imaging device having a radiation detector in the form of a two dimensional array of pixels or pixel elements, each pixel element having a radiation sensor element for detecting radiation incident thereon. An image of a subject may be obtained by the device by projecting radiation onto the detector and determining the relative amounts of radiation incident upon each pixel element over a prescribed time period.
Known detectors include CMOS (complementary metal oxide semiconductor) detectors, CCD (charge coupled device) detectors, image intensifiers and the like. CMOS and CCD detectors are commonly used in domestic hand-held electronic devices such as mobile telephones and video cameras.
Such devices also find application in scientific instrumentation apparatus such as medical imaging systems, electron microscopes including transmission electron microscopes, medical and biological imaging applications, space imaging applications and security applications.
The problem exists that the dynamic range of known detectors is limited. As a consequence, images captured using known detectors frequently suffer the problem that certain regions are underexposed, resulting in relatively high signal to noise ratio, whilst some regions are overexposed, resulting in saturation of the detector. It is desirable to provide a detector having improved dynamic range so that the problem that certain regions are underexposed and other regions are overexposed is reduced or substantially eliminated.
FIG. 1 is a schematic circuit diagram of a known CMOS active pixel element 110. The pixel element 110 has a radiation sensor element in the form of a photodiode 110PD and three MOS transistors: a reset transistor 121, a source-follower input transistor 131 and a selection (‘select’) transistor 141. Source-follower input transistor 131 forms a source follower arrangement with current bias portion 150 which comprises a current mirror arrangement. The source-follower input transistor 131 may also be referred to as a source follower transistor 131.
Each of the transistors 121, 131, 141 has a source, a gate, a drain and a bulk terminal (not shown). In the case that NMOS transistors are employed the bulk terminal may be connected to the common substrate, in the case that PMOS transistors are employed the bulk terminal may be connected to a substantially fixed potential. In some embodiments the bulk terminal may be connected to the source terminal.
The source of the reset transistor 121 is connected to a node X whilst the drain is connected to a supply of potential VRST. The gate of the reset transistor 121 is connected to a reset signal line RST. The gate, source and drain of the source-follower input transistor 131 are respectively connected to node X, the drain of the selection transistor 141 and a supply of reference voltage VDD. The gate of the selection transistor 141 is connected to a row select line ROW and the source of the selection transistor 141 is connected to a column readout line COL.
It is to be understood that the source-follower input transistor 131 is arranged to act as a buffer of the signal applied to the gate thereof. When the current flow through the source-follower input transistor 131 is kept constant by an appropriate bias applied by the current bias portion 150 then, neglecting the second order effect of the activated selection transistor 141, the output voltage on the column readout line COL at terminal T is proportional to the potential applied to the gate of the source-follower input transistor 131 but with a much lower equivalent output impedance.
In operation, reset signal line RST is set HIGH (i.e. assumes a logical 1 condition) causing the reset transistor 121 to turn ON (i.e. the channel of the reset transistor 121 becomes conducting) and a potential Vx of the floating node ‘X’ is set substantially to reset potential VRST. When the potential at Vx is set to VRST, the photodiode 110PD stores charge therein due to the node capacitance of the photodiode 110, a region of space charge associated with the photodiode 110 being increased.
The reset signal line RST is then set LOW (i.e. controlled to assume a logical 0 condition) causing reset transistor 121 to turn OFF.
Radiation incident on the diode 110PD is converted to mobile electron-hole pairs within the diode 110PD causing a current to flow through the diode, discharging the charge accumulated by the photodiode 110PD when the reset signal was applied. This in turn causes a change in Vx.
When it is required to read out Vx the row of the pixel element 110 of FIG. 1 is selected by turning ON the selection transistor 141 (i.e. row line ROW is set HIGH). A signal corresponding to Vx is then applied by the selection transistor 141 to the column line COL which may also be referred to as an output line OUT. The column line COL is in turn connected to a sample-and-hold circuit 160 which presents the potential applied to the column line COL at an output terminal T of the column line COL. The period between application of the reset signal to the photodiode 110PD and the next readout of the potential at node X (when row line ROW is set HIGH) will be referred to herein as the integration period.
At the end of the integration period, following readout of the potential at node X, reset signal line RST is again set HIGH. As discussed above, this has the effect of setting the potential at floating node X to VRST via reset transistor 121, removing charge accumulated by the photodiode 110PD into its node capacitance during the integration period.
Applying VRST to the diode 110PD biases the diode 110PD and therefore VRST may be referred to as a bias voltage. In the embodiment of FIG. 1 VRST is arranged to reverse bias the diode 110PD to increase the width of the depletion layer and improve detection response time.
It is to be understood that in the arrangement of FIG. 1 Vx is monotonically dependant on the cumulative number of photo-generated electrons collected by the diode 110PD, which is in turn typically monotonically dependant on the level of illumination, specifically the illuminance (the total incident luminous flux, per unit area).
When the amount of accumulated charge at the diode 110PD falls to a sufficiently low value Vx ceases to change with further illumination and the diode 110PD may be considered to be ‘saturated’.
It is to be understood that the amount of charge accumulated by the diode 110PD before reaching saturation depends on the node capacitance of the diode 110PD. The larger the node capacitance, the more charge can be accumulated by the diode 110PD before saturation conditions are reached, and the greater the dynamic range (saturation level) of the pixel element 110. However, increasing the node capacitance causes an increase in the sampling noise (reset noise on node X) in the output signal of the pixel element 110 (i.e. the total potential read out at column line COL), reducing the signal to noise ratio (SNR) for relatively small signal levels. It is to be understood that at higher signal levels photon noise (shot noise) may dominate. In the pixel element 110 shown in FIG. 1 a trade-off is made between dynamic range and noise.
In order to increase the dynamic range (saturation level) of the pixel element 110, the element 110 has a switch element 125 coupled to node X which is configured to connect a capacitor device 125C in parallel with the photodiode 110PD when the switch is closed. The switch element 125 may also be referred to as a gain control switch device.
In use, when it is required to increase the dynamic range of the pixel element, the gain control switch 125 is closed. When a reset operation is performed in which the potential at node X is set to VRST, the capacitor 125C accumulates charge together with the photodiode 110PD. Since the capacitance associated with node X is increased, the rate of change of the potential at node X as a function of incident illumination is reduced relative to that when gain control switch 125 is open.
FIG. 1(b) is a signal timing diagram illustrating the application of control signals to the pixel element 110 of FIG. 1(a) in a high gain mode of operation of the element 110 in which gain control switch 125 remains open such that capacitor 125C is not connected across photodiode 110PD.
At time t=t0 the row select signal line ROW is set high and the potential at node X is read out to column line COL. The sample-and-hold circuit 160 samples the potential of the column line COL and maintains output terminal T at this potential whilst readout electronics (not shown) converts this potential to corresponding digital data. Once the potential at node X has been clocked by sample-and-hold circuit 160, at time t1 row select signal line ROW is set low. Also at time t1, row reset line RST is set high and node X is set to the reset potential VRST. Subsequently, at time t2, the potential of row reset line RST is set low, and reset transistor 121 resumes the open condition or state.
Typically the gain control switch 125 is in the form of a transistor device. The present inventors have recognised that in this case, node X has two transistor drains/sources connected to it. Accordingly, two current leak paths exist when the reset transistor 121 and gain switch transistor are in an open condition. The present inventors have identified that this adversely affects one or more characteristics of a detector device having an array of pixel elements 110.
It is desirable to improve the performance of pixel elements used in detector devices.
Embodiments of the present invention endeavour to mitigate at least one of the disadvantages of known radiation detectors.
It is an aim of the present invention to address disadvantages associated with the prior art.